Physical Design FLOW [BLOCK P&R]

PHYSICAL DEESIGN FLOW

• DATAPREPARE                                                                                                                                                
• IMPORTDESIGN / NETLISTIN                                                                                                       
• FLOORPLAN                                                                                                                                       
• PREPLACE                                                                                                                                      
• PLACEMENT                                                                                                                                   
• PRECTSOPT                                                                                                                                     
• CLOCKTREESYNTHESIS                                                                                                                        
• POSTCTSOPTSETUP & POSTCTSOPTHOLD                                                                               
• ROUTE                                                                                                                                                    
• POSTROUTEOPTSETUP & POSTROUTEOPTHOLD                                                                       
• POSTROUTEOPTSI

DataPreapare /ImportDesign

- Prepare data for encounter readable file like
LIB2LDB, power grid configuration file, clock
tree Speck , DONT_USE files


- ImportDesign : load and link gate level netlist

- Check if some of master Cell not found in
Netlist , reported as EMPTY Cell

FLOORPLAN

- I/O Placement


- MACROs Placement


- Spacing among Macros


- Placement Blockage


- Power Planning


- Power Domain Placement

PREPLACE

- Isolate Input/Output Boundary Ports


- Delete Previous Clock Tree [deleteClockTree –

Buffer Tree Removal


- Add Diode on Input post


- Fix location of I/O Buffers & Diodes

PLACEMENT

- Congestion driven or Timing Driven

- Cells are physically Placed

- Check routing Overflow [Horizontal & Vertical
Overflow]


- Return to floorplan stage in case big number
routing Overflow

- No new physical Cells are being inserted at
this stage

PRECTSOPT

• After Placement Timing Optimization [Setup &

• High Fanout Synthesis

CTS/CTSOPTSETUP/CTSOPTHOLD

• Clock Tree Synthesis done to minimize CID &

Skew

• Clock Routing

• Preferred Clock Net are just Below power Metal layer

• Specific Buffers/Inverters for CTS

• At Clock Tree Synthesis no timing Opt

Types of CTS:

CTSOPTSETUP/CTSOPTHOLD 

• After CTS , Setup Uncertainty of Clocks must

be updated

• To check I/O timing Virtual Clock Latencies of

Clocks must be updated

• First Time in flow , Hold optimization will be

done as clocks are propagated after CTS

ROUTING

• Before routing Setup & Hold violations must be under control

• Real routing of signal Nets are done                                                                                                
• Actual Routing Issues will be seen                                                                                                  
• In case major routing issue, need to return at floorplan stage

• Main focus is on Routing net without DRCs

POSTROUTEOPTSETUP/POSTROUTEOPTHOLD

• After Signal routing, could have new timing violations

• Now Clock, Signal are physically routed, so more realistic.

• Setup , Hold, DRV, XTALK Fixing

SIGNOFF

• Physical : LVS, DRC, LFD, ANTENNA, ERC

• Formality

• Extraction , STA

• Timing Model Generation                                                                                                                  
• Power Analysis                                                                                                                                        
• VCLP/MVRC