MULTI VOLTAGE DESIGN:
In a SOC , practically all parts never require same speed, so to save power different parts of SOC work at different voltages. This is called Multi Voltage Design.
Next things come our mind , how we implement the same.
So for that we need to do partition of internal Logic of SOC in different Voltage Domain / Power Domain with each with own Power Supply.
- STA will be complex as timing characterization would be needed at all voltages used in SOC
- Timing path would be from one voltage domain to another voltage domain. so logical hierarchy need to be associated with the power/voltage domain and also timing library would be associated with power domain.
- Multiple power Grid would be required.
-Depending upon requirement , specific sequence of power grid creation would be required.
- To avoid Deadlock during operation , as per architecture particular sequence would be required.
- for tool understanding of power domain , some of standard format like UPF or CPF are required.
In a SOC , practically all parts never require same speed, so to save power different parts of SOC work at different voltages. This is called Multi Voltage Design.
Next things come our mind , how we implement the same.
So for that we need to do partition of internal Logic of SOC in different Voltage Domain / Power Domain with each with own Power Supply.
Challenges In Multi voltage Design:
- LEVEL SIFTER would be required- STA will be complex as timing characterization would be needed at all voltages used in SOC
- Timing path would be from one voltage domain to another voltage domain. so logical hierarchy need to be associated with the power/voltage domain and also timing library would be associated with power domain.
- Multiple power Grid would be required.
-Depending upon requirement , specific sequence of power grid creation would be required.
- To avoid Deadlock during operation , as per architecture particular sequence would be required.
- for tool understanding of power domain , some of standard format like UPF or CPF are required.
LEVEL SHIFTER
As per name , LS is used to change signal from one level to other level. There are two types of level shifter i.e. Low to High and High to Low
- What would happen if not using level shifter , when signal moving from 0.8v to 1.1v ?In this case simultaniousally , nmos and pmos could be on , resulted croubar current.
- Also standard cells works best for rail to rail swing. so in this case significant rise and fall time degradation will happen , resulted performance of standard cell would be degraded.
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