SIGNAL INTEGRITY

Signal Integrity measure quality of electrical Signal. Signal should reach on time and the value of signal must align with desirable value.
How to  minimum impact of Signal  Integrity would be our main Focus.
In physical design , impact of SI can be defied through X-talk Delay and X- Noise.

X-Talk Delay:

XTalk is undesirable phenomenon , caused by coupling capacitance  between victim nets and aggressor nets of chip.  The effect become more dominant as technology shrinks.

A]

B]

In above two picture w2 is victim Net and w1 aggressor net. We can see in both pic , how trans of w1 is affecting tran of w2. This is because of coupling capacitance between net w1 and w2.

In Pic [A], when both nets are rising , because of coupling, net w2  transition would be faster [as  shown in dotted line ] .

In Pic [B],  when aggresson w1 falling and w2 victim net is falling . This case transition net w2 will be slower.

In both case victim nets will get affected only , when both transition happen in the same timing window.

 X-TALK NOISE:

C]

Considering w1 as aggressor and w2 as victim net. w1 is rising and w2 have constant value. Because of coupling capacitance , victim nets gets glitch as shown in dotted line in pic C]

TO Resolve X-Talk: 

• Increase space among victim net and aggressor nets to reduce coupling capacitance.
• To minimize effect of xtalk ,  driver of victim nets could be sized to higher driving strength.  
• By downsizing aggressor of victim net 
• If net length of victim net is long, breaking long net by inserting buffer would resolve the xtalk.

CLOCK GROUP SETTING THAT AFFECT PTSI

Clock Group relationship can be set as :                                                                                                                           

•  EXCLUSIVE PHYSICALLY:      This means both clocks will not be present physically at the same time. So xtalk effect will be neglected for these two clock during PTSI.                                                                                                    
•  EXCLUSIVE LOGICALLY:  Means both clock present  physically, but logically there is no interaction between them. So there would be no valid timing path. As physically present, so x-talk will be computed as normal.      
•  ASYNCHRONOUS:       As clocks are asynchronous , so infinite timing window would be considered between two. That means aggressor can  change any time in the timing window                                                                                                              

Taken Care During P&R flow to Minimize effect of SI

• Avoid narrow channel 
• In narrow channel put partial blockage or soft blockage  or hard blockage. This will depend on how narrow is the channel. But this could affect the timing.
• In case of stacking, leave channels for buffering  to long net and transition fixing.
• set max density of placement to avoid detouring during placement. This max density depends upon designed, typically we set 85%.
• During placement stage no logic cells should be places in soft blockage area.
• Define max tran for the design
• Define Max long net to avoid long nets in design
• Define max local Density\
• Shielding on critical nets