SIGNAL INTEGRITY

Signal Integrity measure quality of electrical Signal. Signal should reach on time and the value of signal must align with desirable value.
How to  minimum impact of Signal  Integrity would be our main Focus.
In physical design , impact of SI can be defied through X-talk Delay and X- Noise.

X-Talk Delay:

XTalk is undesirable phenomenon , caused by coupling capacitance  between victim nets and aggressor nets of chip.  The effect become more dominant as technology shrinks.

A]

B]

In above two picture w2 is victim Net and w1 aggressor net. We can see in both pic , how trans of w1 is affecting tran of w2. This is because of coupling capacitance between net w1 and w2.

In Pic [A], when both nets are rising , because of coupling, net w2  transition would be faster [as  shown in dotted line ] .

In Pic [B],  when aggresson w1 falling and w2 victim net is falling . This case transition net w2 will be slower.

In both case victim nets will get affected only , when both transition happen in the same timing window.

 X-TALK NOISE:

C]

Considering w1 as aggressor and w2 as victim net. w1 is rising and w2 have constant value. Because of coupling capacitance , victim nets gets glitch as shown in dotted line in pic C]

TO Resolve X-Talk: 

• Increase space among victim net and aggressor nets to reduce coupling capacitance.
• To minimize effect of xtalk ,  driver of victim nets could be sized to higher driving strength.  
• By downsizing aggressor of victim net 
• If net length of victim net is long, breaking long net by inserting buffer would resolve the xtalk.

CLOCK GROUP SETTING THAT AFFECT PTSI

Clock Group relationship can be set as :                                                                                                                           

•  EXCLUSIVE PHYSICALLY:      This means both clocks will not be present physically at the same time. So xtalk effect will be neglected for these two clock during PTSI.                                                                                                    
•  EXCLUSIVE LOGICALLY:  Means both clock present  physically, but logically there is no interaction between them. So there would be no valid timing path. As physically present, so x-talk will be computed as normal.      
•  ASYNCHRONOUS:       As clocks are asynchronous , so infinite timing window would be considered between two. That means aggressor can  change any time in the timing window                                                                                                              

Taken Care During P&R flow to Minimize effect of SI

• Avoid narrow channel 
• In narrow channel put partial blockage or soft blockage  or hard blockage. This will depend on how narrow is the channel. But this could affect the timing.
• In case of stacking, leave channels for buffering  to long net and transition fixing.
• set max density of placement to avoid detouring during placement. This max density depends upon designed, typically we set 85%.
• During placement stage no logic cells should be places in soft blockage area.
• Define max tran for the design
• Define Max long net to avoid long nets in design
• Define max local Density\
• Shielding on critical nets 

Advance Lowe Power Design [ Multi Power Domain with Retention ] - 3

Advance Low Power Design - 3 

• Different Power Domain works at different voltages and in above SOC , we want to retail last good state of Design
•  This case , we are not considering switchable domain.
• So we need to have special retention Cells which is called Retention Level Shifter
•  LSINCLP0  > Output clamp to Low , placed in source domain
•  LSINCLP1 >  Output clamp to High, placed in Source Domain
• LSINREL > Output value Latched. Placed in Source Domain 
•  LSOUTCLP0  > Output clamp to Low , placed in Destination Domain
•  LSOUTCLP1 >  Output clamp to High, placed in Destination Domain
• LSOUTREL >    Output value Latched. Placed in Destination Domain

Advance Lowe Power Design [ Multi Power Domain with Switchable Domain] - 2

Low Power Technique 

• In this Case, we need Isolation Cells with Level Shifter for desired clamp value to avoid X state of net between switchable and always on domain.

 Below Pic valid ,when Switchable Domain and Always On Domain have save supply. In this case level Shifter is not required. 

• Even Isolation cells can be placed any domain, but preferable ISO Cells should be placed in Always On domain. In case placing in switchable domain , we need to have always on Power Grids in the domain and ISO  Cells should have Backup supply pins to connect Always On Power Net.                                                                                                                                        
• So We can have two types of Isolation cells depending upon placement location i.e.  Input Isolation & Output ISOLATION.   
• Input Isolation when placed in Power Gated domain  i.e. Switchable Domain.
• Output Isolation when placed in Destination Domain i.e. Always On Domain.
• Some of Output will have more than one destination domain i.e. multi fan-out . For these output signals more than one Output Isolation would be required, but in case of Input Isolation only one Output Signal would be required.  So to be more area efficient , Isolation Signal should be placed in source domain.
• On Input of Switchable blocks, no Isolation cells are required.

When Swichable Domain and Always on Domain works at different voltages , we need to have Level Shifter with Isolation Cells.

ADVANCE LOW POWER TECHNIQUE [Multi Voltage Design with no Switching]

MULTI VOLTAGE DESIGN:

In a SOC , practically all parts never require same speed, so to save  power different parts of SOC work at different voltages.  This is called Multi Voltage Design.

Next things come our mind , how we implement the same.
So for that we need to do partition of internal Logic of SOC in  different Voltage Domain / Power Domain with each with own Power Supply.

Challenges In Multi voltage Design:

- LEVEL SIFTER would be required

- STA will be complex as timing characterization would be needed at all voltages used in  SOC

- Timing path would be  from one voltage domain to another voltage domain. so logical hierarchy need to be associated with the power/voltage domain and also timing library would be associated with power domain.

- Multiple power Grid would be required.

-Depending upon requirement , specific sequence of power grid creation would be required.

- To avoid Deadlock during operation , as per architecture particular sequence would be required.

- for tool understanding of power domain , some of standard format like UPF or CPF are required.

LEVEL SHIFTER 

As per name , LS is used to change signal from one level to other level. There are two types of level shifter i.e. Low to High and High to Low

• What would happen if not using level shifter , when signal moving from 0.8v to 1.1v ?In this case simultaniousally , nmos and pmos could be on , resulted croubar current.                               
• Also standard cells works best  for rail to rail swing.  so in this case significant rise and fall time degradation will happen , resulted performance of standard cell would be degraded.

Physical Design FLOW [BLOCK P&R]

PHYSICAL DEESIGN FLOW

• DATAPREPARE                                                                                                                                                
• IMPORTDESIGN / NETLISTIN                                                                                                       
• FLOORPLAN                                                                                                                                       
• PREPLACE                                                                                                                                      
• PLACEMENT                                                                                                                                   
• PRECTSOPT                                                                                                                                     
• CLOCKTREESYNTHESIS                                                                                                                        
• POSTCTSOPTSETUP & POSTCTSOPTHOLD                                                                               
• ROUTE                                                                                                                                                    
• POSTROUTEOPTSETUP & POSTROUTEOPTHOLD                                                                       
• POSTROUTEOPTSI

DataPreapare /ImportDesign

- Prepare data for encounter readable file like
LIB2LDB, power grid configuration file, clock
tree Speck , DONT_USE files


- ImportDesign : load and link gate level netlist

- Check if some of master Cell not found in
Netlist , reported as EMPTY Cell

FLOORPLAN

- I/O Placement


- MACROs Placement


- Spacing among Macros


- Placement Blockage


- Power Planning


- Power Domain Placement

PREPLACE

- Isolate Input/Output Boundary Ports


- Delete Previous Clock Tree [deleteClockTree –

Buffer Tree Removal


- Add Diode on Input post


- Fix location of I/O Buffers & Diodes

PLACEMENT

- Congestion driven or Timing Driven

- Cells are physically Placed

- Check routing Overflow [Horizontal & Vertical
Overflow]


- Return to floorplan stage in case big number
routing Overflow

- No new physical Cells are being inserted at
this stage

PRECTSOPT

• After Placement Timing Optimization [Setup &

• High Fanout Synthesis

CTS/CTSOPTSETUP/CTSOPTHOLD

• Clock Tree Synthesis done to minimize CID &

Skew

• Clock Routing

• Preferred Clock Net are just Below power Metal layer

• Specific Buffers/Inverters for CTS

• At Clock Tree Synthesis no timing Opt

Types of CTS:

CTSOPTSETUP/CTSOPTHOLD 

• After CTS , Setup Uncertainty of Clocks must

be updated

• To check I/O timing Virtual Clock Latencies of

Clocks must be updated

• First Time in flow , Hold optimization will be

done as clocks are propagated after CTS

ROUTING

• Before routing Setup & Hold violations must be under control

• Real routing of signal Nets are done                                                                                                
• Actual Routing Issues will be seen                                                                                                  
• In case major routing issue, need to return at floorplan stage

• Main focus is on Routing net without DRCs

POSTROUTEOPTSETUP/POSTROUTEOPTHOLD

• After Signal routing, could have new timing violations

• Now Clock, Signal are physically routed, so more realistic.

• Setup , Hold, DRV, XTALK Fixing

SIGNOFF

• Physical : LVS, DRC, LFD, ANTENNA, ERC

• Formality

• Extraction , STA

• Timing Model Generation                                                                                                                  
• Power Analysis                                                                                                                                        
• VCLP/MVRC